utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? features fast access time : 8/10/12/15ns (max.) low operating power consumption: 60 ma (typical.) single 3.3v power supply all inputs and outputs are ttl compatible fully static operation three state outputs package : 28-pin 300 mil soj 28-pin 8mm13.4 mm stsop functional block diagram column i / o column decoder row decoder i/o control logi c control a4 i/o1 v ss v cc we oe ce i/o8 . . . . . . . . . a3 a 12 a7 a6 a5 a8 a 9 a 2 a 1 a 0 a 11 . . . . . . memory array 512 rows 512 columns a 10 a14 a13 pin description symbol description a0 - a14 address inputs i/o1 - i/o8 data inputs/outputs ce chip enable input we write enable input oe output enable input v cc power supply v ss ground general description the ut61l256 is a 262,144-bit high speed cmos static random access memory organized as 32,768 words by 8 bits. it is fabricated using high performance, high reliability cmos technology. the ut61l256 is designed for high-speed system application. it is particularly suited for use in high speed and high density system applications. the ut61l256 operates from a signal 3.3v power supply and all inputs and outputs are fully ttl compatible pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 vcc a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 vss ut61l256 soj 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 ce we oe a13 a14 i/o4 a11 a9 a8 a13 i/o3 a10 a14 a12 a7 a6 a5 vcc i/o8 i/o7 i/o6 i/o5 vss i/o2 i/o1 a0 a1 a2 a4 a3 ut61l256 stsop 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 we oe ce
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to +4.5 v operating temperature t a 0 to +70 storage temperature t stg -65 to +150 power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) tsolder 260 *stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sect ions of this specification is not implied. ex posure to the absolute maximum rating condit ions for extended period may affect device reliability. truth table mode ce oe we i/o operation supply current standby h x x high - z isb, isb1 output disable l h h high - z i cc read l l h d out i cc write l x l d in i cc note: h = v ih , l=v il , x = don't care. dc electrical characteristics (vcc = 3.1v~3.6v, ta = 0 to 70 ) parameter symbol test condition min. max. unit input high voltage v ih 2.0 - v input low voltage v il - 0.8 v input leakage current i li v ss Q v in Q v cc - 1 1 a output leakage current i lo v ss Q v i/o Q v cc ce =v ih or oe =v ih or we = v il - 1 1 a output high voltage v oh i oh = - 4ma 2.2 - v output low voltage v ol i ol = 8ma - 0.4 v - 8 - 90 ma - 10 - 75 ma - 12 - 60 ma operating power supply current i cc ce = v il , i i/o = 0ma ,cycle=min. - 15 - 50 ma i sb ce =v ih - 15 ma standby power supply current i sb1 ce R v cc -0.2v - 3 ma
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? capacitance (ta=25 , f=1.0mhz) parameter symbol min. max unit input capacitance c in - 8 pf input/output capacitance c i/o - 10 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf, i oh /i ol = -4ma/8ma ac electrical characteristics (v cc = 3.1v~3.6v, ta = 0 to 70 ) (1) read cycle parameter symbol ut61l256 -8 ut61l256 -10 ut61l256 -12 ut61l256 -15 unit min. max. min. max. min. max. min. max. read cycle time t rc 8 - 10 - 12 - 15 - ns address access time t aa - 8 - 10 - 12 - 15 ns chip enable access time t ace - 8 - 10 - 12 - 15 ns output enable access time t oe - 3.2 - 5 - 6 - 7 ns chip enable to output in low z t clz* 1 - 2 - 3 - 4 - ns output enable to output in low z t olz* 0 - 0 - 0 - 0 - ns chip disable to output in high z t chz* - 4 - 5 - 6 - 7 ns output disable to output in high z t ohz* - 4 - 5 - 6 - 7 ns output hold from address change t oh 1 - 1 - 3 - 3 - ns (2) write cycle parameter symbol ut61l256 -8 ut61l256 -10 ut61l256 -12 ut61l256 -15 unit min. max. min. max. min. max. min. max. write cycle time t wc 8 - 10 - 12 - 15 - ns address valid to end of write t aw 6 - 8 - 12 - 15 - ns chip enable to end of write t cw 6 - 8 - 12 - 15 - ns address set-up time t as 0 - 0 - 0 - 0 - ns write pulse width t wp 5 - 8 - 9 - 10 - ns write recovery time t wr 0 - 0 - 0 - 0 - ns data to write time overlap t dw 3.5 - 6 - 7 - 8 - ns data hold from end of write time t dh 0 - 0 - 0 - 0 - ns output active from end of write t ow* 1 - 2 - 3 - 4 - ns write to output in high z t whz* - 3.5 - 6 - 7 - 8 ns *these parameters are guaranteed by device char acterization, but not production tested.
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? timing waveforms read cycle 1 (address controlled) (1,2,4) t rc address dout data valid t aa t oh t oh read cycle 2 ( ce and oe controlled) (1,3,5,6) d out address ce oe t rc t aa t ace t oe t clz t olz high-z t ohz t chz data valid high-z t oh notes : 1. we is high for read cycle. 2. device is continuously selected ce =v il. 3. address must be valid prior to or coincident with ce transition; otherwise t aa is the limiting parameter. 4. oe is low. 5. t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 6. at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz.
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? write cycle 1 ( we controlled) (1,2,3,5) d out t wc t aw t cw t wp t ow t as t whz ( 4 ) high-z t dw t dh (4) address ce d in data valid we t wr write cycle 2 ( ce controlled) (1,2,5) high-z (4) data valid d out t wc t aw t cw t wp t whz t as t wr t dw t dh address ce we d in notes : 1. we or ce must be high during all address transitions. 2. a write occurs during the overlap of a low ce and a low we . 3. during a we controlled with write cycle with oe low, t wp must be greater than t whz +t dw to allow the drivers to turn off and data to be placed on the bus. 4. during this period, i/o pins are in the output state, and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after we low transition, the outputs remain in a high impedance state. 6. t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? package outline dimension 28pin 300 mil soj package outline dimension
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? 28 pin 813.4mm stsop package outline dimension
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? ordering information part no. access time (ns) package ut61l256jc-8 8 28 pin soj UT61L256JC-10 10 28 pin soj ut61l256jc-12 12 28 pin soj ut61l256jc-15 15 28 pin soj ut61l256ls-8 8 28 pin stsop ut61l256ls-10 10 28 pin stsop ut61l256ls-12 12 28 pin stsop ut61l256ls-15 15 28 pin stsop
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? revision history revision description date rev. 1.0 original. rev 1.1 release version oct. 21,1999 rev 1.2 oct ,2000 rev 1.3 1. the [ackage name of tsop-1 is revised as stsop. 2. the symbols ce#,oe# and we# are revised as ce , oe and we may 15,2001
utron ut61l256 rev. 1.3 32k x 8 bit high speed low v cc cmos sram utron technology inc. p80023 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? this page is left blank intentionally.
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